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Learn how to root cause of intermittent problems when running NVMe Validation tests.
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Learn how to debug high latency bursts in Data Center workloads.
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Learn challenges and mitigation strategies for managing hardware- and firmware-level risks.
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Use our patented "Memory fencing" technology to detect functional errors that occur when a device with accesses memory space outside of the area specified by the device driver.
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This paper will establish a practical range for the time constants that we need to cover and will illustrate the effectiveness of DSP-based corrections for a few selected time-constant values.
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This paper discusses analog-to-digital converter (ADC) resolution (mostly with regard to oscilloscopes)
and considerations for improving resolution using various ADC deployment methods.
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The fastest electrical PAM-4 signal is demonstrated. The technology behind the generation of this signal
along with the acquisition of the signal is discussed along with the motivation for generating signals like
this in optical communications research.
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Power distribution network testing and validation is an important task in the system design flow. To avoid
unnecessary testing time, the measurement setup, the instruments and the connections should be reusable
for different tasks. Instruments and setups, therefore, whether they work in the time domain or frequency
domain, limit the number of functions that can be performed without changing instruments, or cables or
connections. The paper explores test setups and instrumentations that allow multiple tests being performed
without changing the hardware connections. Real-life test results will illustrate the benefits and limitations
of the setup.
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